The disclosure relates to delay lock loop circuits and/or phase locked loop circuits and more particularly to such circuits that employ lock and/or unlock detection.
Feedback controlled clock generating circuits, such as phase locked loop circuits (PLL) and delay locked loop circuits (DLL) are known for use in integrated circuits that require clock sources. Phase locked loop circuits, for example, lock to a desired clock frequency and as shown in FIG. 1, they typically include a phase frequency detector 100, a charge pump 102, a low pass filter 103, a voltage controlled oscillator 104, a loop divider 106 and a frequency based clock lock and unlock detector 108. Such frequency base lock and unlock detectors typically provided coarse directional change detection and coarse clock unlock detection by generating a coarse frequency based unlock signal 110 to core logic 112 that utilized the generated output clock 114 generated from the PLL. The core logic 112 such as a processor core or other suitable circuit responded to the coarse unlock signal by shutting down or performing other operations since it was informed that it could not trust the generated clock signal 114.
The phase frequency detector 100 receives a reference frequency 116 as input from a suitable reference frequency generator, and also received the feedback reference frequency 118 fed back from, for example, the loop divider 106. The phase frequency detector generates up and down frequency detection signals 120 and 122 to the charge pump 102 to control the voltage controlled oscillator 104 to maintain a constant output clock frequency 114 as known in the art. The frequency based lock and unlock detector 108 was responsive to the up and down control signals 120 and 122 to detect the change in frequency provided by the phase frequency detector 100. However, such frequency based lock and unlock detectors typically provided only a coarse unlock detection so that the logic core 112 was unable to determine whether the reason for the unlocked clock output 114 was due to a frequency error, phase error, or other error. A frequency based lock and unlock detector 108 may employ, for example, a counter that counts the amount of time the PLL is not locked such as single coarse unlock signal 110 is typically provided.
FIG. 2 illustrates one example of a PLL unlock detector circuit as known in the art. In this example, the coarse PLL unlock signal 110 is generated using an unlock detector circuit 200 that employs up and down reference clock and feedback clock latches 202, corresponding multiplexers 204 and 206, and logic elements 208 and 210 that are coupled to OR gate 212. As to the unlock detector, in one example the PLL has a built-in unlock-detector 108 that provides flags to an ASIC 112 about the locking-status of the PLL. This detector output, O_UNLOCK, will indicate a logic “0” and a logic “1” when the PLL is in the “lock” and “unlock” state, respectively. The accuracy can be adjusted by IUNLOCK_DET according to table 1 below. The functional table is presented in table 2. Setting IUNLOCK_DET to zero bypasses the unlock detector circuit. IUNLOCK_SEL can be used to select the 50% (depends on duty cycle of reference clock source at input of PFD) or 100% (1 complete clock cycle) phase error detection. (IUNLOCK_SEL_SYS=1 for 100% and IUNLOCK_SEL_SYS=0 for 50%). The accuracy of the detected phase error depends on the input reference clock's duty cycle. For example, if the reference clock's duty cycle is 30%, any phase error bigger than 30% of reference clock's period will be detected as an unlock state. IUNLOCK_DET—32—[3:0] value indicates the number of consecutive unlock signals detected during multiple reference clock cycles (i.e. if IUNLOCK_DET—32—[3:0]=0111, and unlock signal is flagged, the phase error has been bigger than 50% of REF clock's period for seven conservative clock cycles.)
As shown in FIG. 2. UP and DN signals generated by PFD are sampled at the falling edge of REF and FB clocks. Depending on the PFD topology there is a minimum UP/DN pulse width which may be sampled as a wrong unlock situation. The minimum UP/DN pulse is estimated as 2 ns therefore the sampling clock should be high more than 2 ns. For example if the REF clock is running at 50 MHz (period 20 ns) the duty cycle should not be worst than 10%-90% otherwise the minimum UP pulse can be detected as unlock signal.) The logic element 208 counts a number of offsets for the REF clock and the logic element 210 counts the number of offsets of the FB clk and an unlock condition signal is output if the counts exceed a set number. However, this is merely a coarse frequency unlock condition detector.
A need exists for an improved PLL or DLL lock and/or unlock detection circuit.